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 Ordering number : EN5330
CMOS LSI
LC75372E
Electronic Volume Control for Car Stereo Systems
Overview
The LC75372E is an electronic volume control that can implement volume, balance, fader, bass/treble, loudness, input switching, and input level control functions with a minimal number of external components.
* Built-in reference voltage generation circuit * Serial data input: Supports CCB format communication with the system controller.
Package Dimensions
unit: mm 3148-QFP44MA
[LC75372E]
Features
* Volume: Provides 81 positions, from 0 dB to -79 dB (in 1-dB steps) and -. A balance function can be implemented by controlling the left and right channels independently. * Fader: This function can attenuate either the rear or the front outputs over 16 positions. (From 0 to -20 dB in 2-dB steps, from -20 to -25 dB in one 5-dB step, from -25 to -45 dB in 10-dB steps, -60 dB, and -.) * Bass/treble: Forms an NF-type tone control circuit (LUX type) with the addition of external capacitors. The base and treble controls each have 15 positions. * Loudness: The volume resistor ladders are tapped starting at the -20-dB position. A loudness function can be implemented by adding external RC circuits at these taps. * The signal can be selected from one of three inputs for each of the left and right channels. The input signals can be amplified from 0 to +18 dB in 6-dB steps. * On-chip buffer amplifiers for a minimum of external components. * Minimal switching noise due to fabrication in a silicongate CMOS process.
SANYO: QIP44MA
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Maximum input voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max Pd max Topr Tstg VDD CL, DI, CE, LIN, RIN, LFIN, RFIN, L1 to L3, R1 to R3 Ta 85C Conditions Ratings 11 VSS - 0.3 to VDD + 0.3 260 -40 to +85 -50 to +125 Unit V V mW C C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
41596HA (OT) No. 5330-1/18
LC75372E Allowable Operating Ranges at Ta = 25C, VSS = 0 V
Parameter Supply voltage Input high-level voltage Input low-level voltage Input voltage amplitude Input pulse width Setup time Hold time Operating frequency Symbol VDD VIH VIL VIN toW tsetup thold fopg VDD CL, DI, CE CL, DI, CE CL, DI, CE, LIN, RIN, LFIN, RFIN, L1 to L3, R1 to R3 CL CL, DI, CE CL, DI, CE CL Conditions min 6.0 4.0 VSS VSS 1 1 1 500 typ max 10.0 VDD 1.0 VDD Unit V V V Vp-p s s s kHz
Electrical Characteristics at Ta = 25C, VDD = 9 V, VSS = 0 V
Parameter [Input Block] Input resistance Minimum input gain Maximum input gain Step resolution [Volume Control Block] Input resistance Step resolution Step error [Fader Volume Block] Input resistance Rfed LFIN, RFIN step = 0 to -20 dB Step resolution ATstep step = -20 to -25 dB step = -25 to -45 dB Step error Output load resistance [Bass/Treble Control Block] Bass control range Treble control range [Overall Characteristics] Total harmonic distortion Crosstalk Output at maximum attenuation THD (1) THD (2) CT VO min VN (1) VN (2) IDD IIH IIL VCL VIN = 1 Vrms, f = 1 kHz, all settings flat overall VIN = 1 Vrms, f = 20 kHz, all settings flat overall VIN = 1 Vrms, f = 1 kHz, all settings flat overall, Rg = 1 k VIN = 1 Vrms, f = 1 kHz, main volume at - VIN = 1 Vrms, f = 1 kHz, main volume at -, INMUTE All settings flat overall (IHF-A), Rg = 1 k All settings flat overall (DIN-AUDIO), Rg = 1 k VDD - VSS = 10 V CL, DI, CE: VIN = 9 V CL, DI, CE: VIN = 0 V All settings flat overall, measurement point; fader output THD = 1%, RL = 10 K -10 2 0.045 0.040 80 -78 -81 15 20 25 30 40 30 10 % % dB dB dB V V mA A A Vrms Gbass Gtre Max. boost/cut Max. boost/cut 9 8 10.5 10.5 12 13 dB dB ATerr RL step = 0 to -45 dB step = -45 to -60 dB LFOUT, LROUT, RFOUT, RROUT -2 -3 10 12 20 2 5 10 0 0 +2 +3 28 k dB dB dB dB dB k Rv10 Rv1 ATstep ATerr step = 0 to -20 dB step = -20 to -50 dB -1 -3 L10dBIN, R10dBIN: 10-dB steps, loudness off LIN, RIN: 1-dB steps 30 12 50 20 1 0 0 +1 +3 70 28 k k dB dB dB Rin Gin min Gin max Gstep L1 to L3, R1 to R3 30 -2 +16.0 50 0 +18.0 +6.0 70 +2 +20.0 k dB dB dB Symbol Conditions min typ max Unit
Output noise voltage Current drain Input high-level current Input low-level current Maximum input level
No. 5330-2/18
LC75372E Equivalent Circuit Block Diagram and Sample Application Circuit
No. 5330-3/18
LC75372E Electrical Characteristics Test Circuits 1. Total harmonic distortion
No. 5330-4/18
LC75372E 2. Output noise voltage
No. 5330-5/18
LC75372E 3. Crosstalk
No. 5330-6/18
LC75372E Pin Assignment
No. 5330-7/18
LC75372E Pin Functions
Pin No. Symbol Equivalent I/O circuit Function
* Common pins for the main volume block, fader volume block, tone block, gain control block, and input switching block. 40 38 LVref RVref * Since the capacitors connected between LVref/RVref and VSS become the residual resistance when the volume control is at maximum attenuation, the values of these capacitors must be chosen carefully. * The applied voltage must never exceed VDD.
39
Vref
0.488 VDD voltage generation block. A capacitor must be connected between Vref and VSS to suppress power supply ripple.
41 42 37 36
LROUT LFOUT RROUT RFOUT * Fader outputs. The front and rear systems can be attenuated independently. The amount of attenuation is the same in the left and right channels. * Low impedance operational amplifier outputs
43 35
LFIN RFIN
* Fader inputs * Must be driven from low-impedance circuits.
44 34
LOUT ROUT
Tone control outputs
3 2 1 31 32 33 7 6 27 28
LT1 LT2 LT3 RT1 RT2 RT3 LCT1 LCT2 RCT1 RCT2 Loudness pins. Connect high-band compensation capacitors between LCT1/RCT1 and L10dBIN/R10dBIN, and connect low-band compensation capacitors between LCT2/RCT2 and LVref/RVref. Connections for the bass and treble compensation capacitors for the tone control circuit Connect high-band compensation capacitors between T1 and T2. Connect low-band compensation capacitors between T2 and T3.
Continued on next page. No. 5330-8/18
LC75372E
Continued from preceding page.
Pin No. Symbol Equivalent I/O circuit Function
8 26
L10dBIN R10dBIN
* 10-dB volume control inputs * These inputs must be driven from low-impedance circuits.
9 25
LSELO RSELO
Outputs from the input selector
13 12 10 21 22 24
L1 L2 L3 R1 R2 R3 Signal inputs
14 19
VDD VSS
Power supply connection Ground Chip enable. Data is latched internally at the point this pin goes from high to low. The analog switches operate at that point. Data transfer is enabled when this pin is high.
15
CE
16 17 20 5 29 4 30 11 18 23
DI CL TEST L10dBOUT R10dBOUT LIN RIN
Inputs for the serial data and clock used for LSI control. Test input (Must be left open during normal operation.) 10-dB block outputs * 1-dB block inputs * These inputs must be driven by low-impedance circuits.
NC
No-connection pins.
No. 5330-9/18
LC75372E Input Block Equivalent Circuit
Main Volume Control Equivalent Circuit
No. 5330-10/18
LC75372E Tone Control Block Equivalent Circuit
No. 5330-11/18
LC75372E Fader Volume Control Block Equivalent Circuit
No. 5330-12/18
LC75372E Sample Calculation of the Loudness Circuit External Constants First, see the LC75372E 10-dB step internal equivalent circuit shown on page 10. Figure 1 shows a circuit to which the loudness circuit external components have been added, and which has been simplified for this calculation. The sample calculation below uses this circuit diagram to acquire a 5-dB boost at f = 100 Hz. (f = 100 Hz, 5-dB boost) Assuming that the resistors and capacitors in Figure 1 have the following values: R1 = R2 = 50 k R3 = 5 k And C1 = Z1 and C2 = Z2. Then: R2 (R3 + Z2) R2 + R3 + Z2 = -20 dB VOUT = R1 * Z1 R2 (R3 + Z2) + (at = 1 kHz) R1 + Z1 R2 + R3 + Z2 R2 (R3 + 10 * Z2) R2 + R3 + 10 * Z2 = -15 dB VOUT = R2 (R3 + 10 * Z2) R1 * 10 * Z1 + (at = 100 Hz) R1 + 10 * Z1 R2 + R3 + 10 * Z2 From the above equations we find: Z1 891.5 k and Z2 = 880 . Therefore, the specifications will be met if capacitors that have these impedances at f = 1 kHz are connected externally. The result is that C1 = 178.5 pF and C2 = 0.18 F.
Figure 1
No. 5330-13/18
LC75372E Control System Timing and Data Format The LC75372E is controlled by applying data in the stipulated format to the CE, CL, and DI pins. The data consists of 40 bits, of which 8 bits are the chip address and 32 bits are the data.
Note: The bits D19 and D28 to D31 are LSI test bits, and must be set to 0.
No. 5330-14/18
LC75372E
No. 5330-15/18
LC75372E
No. 5330-16/18
LC75372E
No. 5330-17/18
LC75372E
Usage Notes 1. The states of the internal analog switches are undefined when power is first applied. Use an external muting circuit or other technique to mute the outputs until correct control data has been set up in the LC75372E. 2. Either cover the lines connected to the CL, DI, and CE pins with the ground pattern or use shielded cable for those lines to prevent the high-frequency digital signals on those lines from entering the analog system. 3. Muting by input switching must be used in conjunction with the volume control setting when the maximum volume control attenuation (the VOL = - position) is used.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 1996. Specifications and information herein are subject to change without notice. PS No. 5330-18/18


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